1. Field of the Invention
This invention relates to computer memory devices, and more particularly, to a pulse wordline (PWL) control circuit and method for a computer memory device such as a DRAM (dynamic random-access memory) device or an SRAM (static random-access memory) device.
2. Description of Related Art
Random-access memory (RAM) is a volatile memory that allows data to be written thereto and read therefrom at any time during operation of the computer system. There are two major types of RAMs: SRAM (static random-access memory) and DRAM (dynamic random access memory). Whether an SRAM cell stores a binary value of 1 or 0 is dependent on the ON/OFF state of a transistor element therein; and in the case of a DRAM cell, it is dependent on whether a capacitor element therein is fully charged or discharged.
DRAMs are generally slower in speed than SRAMs. However, since DRAMs are typically higher in density and lower in manufacturing cost, they are more widely used as the primary memory of most computer systems than SRAMs. In the operation of a DRAM device, whether a certain memory cell is to be set to store 1 or 0 is controlled by a peripheral read/write circuit that controls the charging and discharging of the capacitor element of that memory cell.
FIG. 1 is a schematic diagram showing the equivalent circuit structure of each memory cell of a typical DRAM device, which includes a transfer field effect transistor (TFET) T and a data storage capacitor C. The TFET T is formed in such a manner that its gate is connected to a word line WL, its source is connected to a bit line BL, and its drain is connected to one electrode 12 of the capacitor C. The opposing electrode 10 of the capacitor C is connected to a fixed voltage source. The capacitor C further includes a dielectric layer 14 disposed between the two electrodes 10 and 12. Whether the memory cell stores a binary data bit 0 or 1 is dependent on whether the capacitor C is fully charged or discharged. For example, if the capacitor C is fully charged, it provides a high voltage that represents the storage of a binary value 1 thereon, whereas when fully discharged, it provides a null voltage that represents the storage of a binary value 0 thereon. Moreover, the access to the capacitor C, whether read or write, is controlled by the TFET T whose ON/OFF state is further controlled by the logic state of the wordline WL. When the wordline WL is activated to a high-voltage logic state, it switches on the TFET T, whereas when the wordline WL is deactivated to a low-voltage logic state, it switches off the TFET T.
It can be learned from the foregoing description that the access operation to the data storage capacitor C is controlled by the logic state of the wordline WL. When the TFET T is switched on, the capacitor C is connected to the bitline BL, thus allowing the current charge condition of the capacitor C to be transferred to the bitline BL.
Conventionally, a RC (resistor-capacitor) delay circuit is utilized for controlling the high/low logic state of the wordlines of the memory device. One drawback to this scheme, however, is that, when process parameters are changed to alter the RC value, it can cause the wordlines to be deactivated to the low-voltage logic state before the data stored in the memory cell is completely detected by the sense amplifier (SA). The detected data can therefore be erroneous. One solution to this problem is to provide an adequate window for the changes in the process parameters. However, the allowable window size decreases as the operating frequency of memory device is increased. Therefore, the improvement by this solution to the problem is still limited. This problem is depicted in more detail in the following with reference to FIG. 2.
FIG. 2 is a schematic block diagram of a memory device utilizing a conventional PWL control method. As shown, the memory device includes an address decoder 20, a delay circuit 22 such as an RC circuit, an array of memory cells 24, a sense amplifier 26, and an output buffer 28. During access operation, the address decoder 20 decodes an address signal and then transfers the decoded address signal to the RC delay circuit 22 where the decoded address signal is delayed by a predetermined period. When a certain wordline is set to a high-voltage logic state by the decoded address signal, the data stored in the associated memory cell in the array 24 will be accessed and detected by the sense amplifier 26. The sense amplifier 26 then transfers the sensed data via the output buffer 28 to the external circuit that requested the data.
When there are changes in the process parameters, for example when the capacitor area for the RC delay circuit 22 is downsized, it will cause the delay time by the RC delay circuit 22 to be shortened, thus resulting in an early deactivation of the activated wordline before the current voltage state that represents the data stored in the accessed memory cell is completely detected by the sense amplifier 26. Hence, the detected data by the sense amplifier 26 can be erroneous.
In conclusion, the prior art has the following disadvantages.
(1) First, the detected data by the sense amplifier can be erroneous when the memory device is downsized, which results in a reduced RC value to the RC delay circuit, which in turn results in an early deactivation of the currently activated wordlines before the data is completely detected by the sense amplifier. PA1 (2) Second, the scheme of designing a window as a solution to the foregoing problem is nevertheless restricted by the operating frequency of the memory device, in that the allowable window size decreases as the operating frequency of memory device is increased. Therefore, the improvement on the problem is still limited.